Vivado/Vitis

The Vivado and Vitis backends are intended for use with AMD/Xilinx FPGAs. The Vivado backend targets the discontinued Vivado HLS compiler, while the Vitis backend targets the Vitis HLS compiler. Both are designed to produce IP for incorporation in Vivado designs. (See VivadoAccelerator for generating easily-deployable models with Vivado HLS.) The Vitis accelerator flow is not directly supported, though HLS code produced with the Vitis backend can be easily incorporated into a Vitis kernel.

Users should generally use the Vitis backend for new designs that target AMD/Xilinx FPGAs; new hls4ml developments will not necessarily be backported to the Vivado backend.

Known issues

• With Vitis HLS 2023.2, recurrent layers (SimpleRNN, LSTM, GRU) may not meet the target clock at the default clock uncertainty when they use io_stream and the Latency strategy, or the Resource strategy with a reuse factor of 1. Vitis HLS 2024.1 is not affected. With 2023.2, raising the clock uncertainty to 35% (clock_uncertainty='35%') was enough for the models tested, at the cost of one to three extra clock cycles per time step.

Fused strategy

The Vitis backend also provides Strategy: Fused, which computes a chain of Dense layers together so that consecutive layers run at the same time. See Fused Strategy.