hls4ml.backends.vitis package

Subpackages

• hls4ml.backends.vitis.passes package
  • Submodules
  • hls4ml.backends.vitis.passes.feature_check module
    • ValidateConvImplementation
      • ValidateConvImplementation.match()
      • ValidateConvImplementation.transform()
    • ValidateFusedIoType
      • ValidateFusedIoType.match()
      • ValidateFusedIoType.transform()
    • ValidateResourceStrategy
      • ValidateResourceStrategy.match()
      • ValidateResourceStrategy.transform()
    • ValidateResourceUnrolledStrategy
      • ValidateResourceUnrolledStrategy.match()
      • ValidateResourceUnrolledStrategy.transform()
    • ValidateStdCppTypes
      • ValidateStdCppTypes.match()
      • ValidateStdCppTypes.transform()
  • hls4ml.backends.vitis.passes.fifo_depth_optimization module
    • FifoDepthOptimization
      • FifoDepthOptimization.transform()
    • FifoDepthOptimizationPost
      • FifoDepthOptimizationPost.get_hls_project_path()
      • FifoDepthOptimizationPost.transform()
    • FifoDepthOptimizationProfile
      • FifoDepthOptimizationProfile.transform()
    • generate_depths_file()
    • get_vitis_optimized_fifo_depths()
    • initialize_large_fifos()
    • set_optimized_fifo_depths()
  • hls4ml.backends.vitis.passes.fuse_dense module
    • FoldActivationIntoFused
      • FoldActivationIntoFused.match()
      • FoldActivationIntoFused.transform()
    • LayoutFusedDotWeights
      • LayoutFusedDotWeights.match()
      • LayoutFusedDotWeights.transform()
    • PlanDenseFusion
      • PlanDenseFusion.transform()
    • SubstituteUnfusedStrategy
      • SubstituteUnfusedStrategy.match()
      • SubstituteUnfusedStrategy.transform()
    • ValidateDenseFusion
      • ValidateDenseFusion.transform()
  • hls4ml.backends.vitis.passes.fused_templates module
    • DenseFusedConfigTemplate
      • DenseFusedConfigTemplate.format()
      • DenseFusedConfigTemplate.match()
    • DenseFusedFunctionTemplate
      • DenseFusedFunctionTemplate.format()
      • DenseFusedFunctionTemplate.match()
  • Module contents

Submodules

hls4ml.backends.vitis.vitis_backend module

class hls4ml.backends.vitis.vitis_backend.VitisBackend(name='Vitis')

Bases: VivadoBackend

build(model, reset=False, csim=True, synth=True, cosim=False, validation=False, export=False, vsynth=False, fifo_opt=False, log_to_stdout=True, pnr=False)

Build the HLS project, running the steps that are enabled.

Parameters:

• model (ModelGraph) – The model to build.

• reset (bool, optional) – Start a new HLS project, removing the previous one. Defaults to False.

• csim (bool, optional) – Run C simulation. Defaults to True.

• synth (bool, optional) – Run C synthesis. Defaults to True.

• cosim (bool, optional) – Run C/RTL co-simulation. Defaults to False.

• validation (bool, optional) – Compare the outputs of C simulation and co-simulation. Defaults to False.

• export (bool, optional) – Export the design as an IP. Defaults to False.

• vsynth (bool, optional) – Synthesize the generated Verilog with Vivado, out of context. If synthesis leaves the cascade input of a DSP unconnected (design rule DSPS-2), the design is synthesized again with -cascade_dsp tree, which can change the resources. Defaults to False.

• fifo_opt (bool, optional) – Record the FIFO occupancy during co-simulation, used by the FIFO depth optimization flow. Defaults to False.

• pnr (bool, optional) – Also place and route the design after Vivado synthesis, for the resources, timing and power after implementation. Vivado estimates the power from default switching activity, not from a simulation of the design, so most of the total can be the static power of the device. Implies vsynth. Defaults to False.

Returns:

The reports read from the project, see hls4ml.report.parse_vivado_report.

Return type:

dict

Raises:

Exception – If vivado_hls is not on PATH, or if a step of the build fails.

build_stitched_design(model, stitch_design=True, sim_stitched_design=False, export_stitched_design=False, graph_reports=None, simulation_input_data=None)

create_initial_config(part='xcvu13p-flga2577-2-e', clock_period=5, clock_uncertainty='27%', io_type='io_parallel', namespace=None, write_weights_txt=True, write_tar=False, write_emulation_constants=False, tb_output_stream='both', **_)

Create initial configuration of the Vitis backend.

Parameters:

• part (str, optional) – The FPGA part to be used. Defaults to ‘xcvu13p-flga2577-2-e’.

• clock_period (int, optional) – The clock period. Defaults to 5.

• clock_uncertainty (str, optional) – The clock uncertainty. Defaults to 27%.

• io_type (str, optional) – Type of implementation used. One of ‘io_parallel’ or ‘io_stream’. Defaults to ‘io_parallel’.

• namespace (str, optional) – If defined, place all generated code within a namespace. Defaults to None.

• write_weights_txt (bool, optional) – If True, writes weights to .txt files which speeds up compilation. Defaults to True.

• write_tar (bool, optional) – If True, compresses the output directory into a .tar.gz file. Defaults to False.

• write_emulation_constants (bool, optional) – If True, write constants to define.h useful for emulation. Defaults to False.

• tb_output_stream (str, optional) – Controls where to write the output. Options are ‘stdout’, ‘file’ and ‘both’. Defaults to ‘both’.

Returns:

initial configuration.

Return type:

dict

Module contents