XLS

The XLS backend can convert hls4ml models into Verilog or SystemVerilog via Google XLS, which can be converted to IP via Vivado or other tools.

To enable XLS:

pip install hls4ml[xls]

hls4ml uses pyxls package to access XLS API. pyxls comes with batteries included, and a separate XLS installation is not required.

Workflow

XLS backend performs the following transformations:

hls4ml representation -> DSLX (<ProjectName>.x) -> XLS IR (<ProjectName>.ir) -> Optimized XLS IR (<ProjectName>.opt.ir) -> (System)Verilog (<ProjectName>.sv)

DSLX is a DSL with Rust-like syntax. DSLX project generated by hls4ml in <OutputDir>/firmware contains the main module <ProjectName>.x, layer modules layer_<LayerName>.x, and helper modules in ap_types/ and nnet_utils/. You may work with this project either through hls4ml or using your own XLS toolchain.

hls4ml calls XLS compiler to convert DSLX into XLS IR format (<ProjectName>.ir) and then runs IR optimization passes (<ProjectName>.opt.ir).

Then, hls4ml uses XLS Codegen to generate (System)Verilog (<ProjectName>.sv) from IR.

You can override default codegen options: .. code-block:: python

config = hls4ml.utils.config_from_keras_model(model) # This sets hls_model.config[‘XLSCodegenFlags’] hls_model = hls4ml.converters.convert_from_keras_model(

model, hls_config=config, backend=’XLS’, xls_codegen_flags={‘delay_model’: ‘asap7’, ‘generator’: ‘pipeline’, ‘use_system_verilog’: False}

)

An example Vivado script for generating IP from RTL can be found at <OutputDir>/build_prj.tcl.

I/O Types and Strategy

Currently, only io_parallel is supported. Strategy is ignored. All operations are fully unrolled.

Since XLS supports only signed FixedPoint type (similar to ap_fixed), all unsigned types are converted to signed types (with extra bit added).