hls4ml.backends.vivado_accelerator package

Subpackages

• hls4ml.backends.vivado_accelerator.passes package
  • Submodules
  • hls4ml.backends.vivado_accelerator.passes.fifo_depth_optimization module
    • FifoDepthOptimization
      • FifoDepthOptimization.transform()
  • Module contents

Submodules

hls4ml.backends.vivado_accelerator.vivado_accelerator_backend module

class hls4ml.backends.vivado_accelerator.vivado_accelerator_backend.VivadoAcceleratorBackend

Bases: VivadoBackend

build(model, reset=False, csim=True, synth=True, cosim=False, validation=False, export=False, vsynth=False, fifo_opt=False, bitfile=False, pnr=False)

Build the HLS project, running the steps that are enabled.

Parameters:

• model (ModelGraph) – The model to build.

• reset (bool, optional) – Start a new HLS project, removing the previous one. Defaults to False.

• csim (bool, optional) – Run C simulation. Defaults to True.

• synth (bool, optional) – Run C synthesis. Defaults to True.

• cosim (bool, optional) – Run C/RTL co-simulation. Defaults to False.

• validation (bool, optional) – Compare the outputs of C simulation and co-simulation. Defaults to False.

• export (bool, optional) – Export the design as an IP. Defaults to False.

• vsynth (bool, optional) – Synthesize the generated Verilog with Vivado, out of context. If synthesis leaves the cascade input of a DSP unconnected (design rule DSPS-2), the design is synthesized again with -cascade_dsp tree, which can change the resources. Defaults to False.

• fifo_opt (bool, optional) – Record the FIFO occupancy during co-simulation, used by the FIFO depth optimization flow. Defaults to False.

• pnr (bool, optional) – Also place and route the design after Vivado synthesis, for the resources, timing and power after implementation. Vivado estimates the power from default switching activity, not from a simulation of the design, so most of the total can be the static power of the device. Implies vsynth. Defaults to False.

Returns:

The reports read from the project, see hls4ml.report.parse_vivado_report.

Return type:

dict

Raises:

Exception – If vivado_hls is not on PATH, or if a step of the build fails.

create_initial_config(board='pynq-z2', part=None, clock_period=5, clock_uncertainty='12.5%', io_type='io_parallel', interface='axi_stream', driver='python', input_type='float', output_type='float', platform='xilinx_u250_xdma_201830_2')

Create initial accelerator config with default parameters

Parameters:

• board – one of the keys defined in supported_boards.json

• clock_period – clock period passed to hls project

• io_type – io_parallel or io_stream

• interface – axi_stream: generate hardware designs and drivers which exploit axi stream channels. axi_master: generate hardware designs and drivers which exploit axi master channels. axi_lite : generate hardware designs and drivers which exploit axi lite channels. (Don’t use it to exchange large amount of data)

• driver – python: generates the python driver to use the accelerator in the PYNQ stack. c: generates the c driver to use the accelerator bare-metal.

• input_type – the wrapper input precision. Can be float or an ap_type. Note: VivadoAcceleratorBackend will round the number of bits used to the next power-of-2 value.

• output_type – the wrapper output precision. Can be float or an ap_type. Note: VivadoAcceleratorBackend will round the number of bits used to the next power-of-2 value.

• platform – development target platform

Returns:

populated config

get_default_flow()

The name of the default flow of the backend.

Default flow is used as the conversion target if the target flow has not been specified.

get_writer_flow()

make_xclbin(model, platform='xilinx_u250_xdma_201830_2')

Create the xclbin for the given model and target platform.

Parameters:

• model (ModelGraph) – Compiled and build model.

• platform (str, optional) – Development/Deployment target platform, must be installed first. The host machine only requires the deployment target platform. Refer to the Getting Started section of the Alveo guide. Defaults to ‘xilinx_u250_xdma_201830_2’.

hls4ml.backends.vivado_accelerator.vivado_accelerator_config module

class hls4ml.backends.vivado_accelerator.vivado_accelerator_config.VivadoAcceleratorConfig(config, model_inputs, model_outputs)

Bases: object

get_board()

get_board_info(board=None)

get_clock_period()

get_corrected_types()

get_driver()

get_driver_file()

get_driver_path()

get_input_type()

get_interface()

get_io_bitwidth()

get_krnl_rtl_src_dir()

get_output_type()

get_part()

get_platform()

get_tcl_file_path()

Module contents