hls4ml.backends.coyote package

Subpackages

hls4ml.backends.coyote.passes package

Submodules

hls4ml.backends.coyote.coyote_backend module

class hls4ml.backends.coyote.coyote_backend.CoyoteBackend

Bases: VitisBackend

The Coyote backend, which deploys hls4ml models on a PCIe-attached Alveo FPGA Underneath it uses the Coyote shell: https://github.com/fpgasystems/Coyote, which offers high-performance data movement, networking capabilities, multi-tenancy, partial reconfiguration etc. This backend has some similarities with the VitisAccelerator backend, but the underlying platforms are different. The implementation of this backend remains mostly simple, inheriting most of the functionality from the Vitis backend and providing the necessary infrastructure to run model inference on Alveo boards.

Currently, this backend supports batched inference of a single model on hardware. In the future, it can easily be extended with the following capabilities, leveraging Coyote’s features:

Distributed inference

Multiple parallel instances of hls4ml models (same or distinct models)

Dynamic, run-time reconfiguration of models

Generic examples of Coyote can be found at the above-mentioned repository, under examples/

build(model, device: str = 'u55c', aclk_freq: float = 250, reset: bool = False, csim: bool = True, synth: bool = True, cosim: bool = False, validation: bool = False, csynth: bool = False, bitfile: bool = False, timing_opt: bool = False, hls_clock_period: float = 4, hls_clock_uncertainty: float = 27)

Synthesizes the hls4ml model bitstream as part of the Coyote shell and compiles the host-side software to control the FPGA and run model inference

Parameters:

model (ModelGraph) – hls4ml model to synthesize
device (str, optional) – Target Alveo FPGA card; currently supported u55c, u280 and u250
aclk_freq (float, optional) – System/shell clock frequency
reset (bool, optional) – Reset HLS project, if a previous one is found
csim (bool, optional) – Run C-Simulation of the HLS project
synth (bool, optional) – Run HLS synthesis
cosim (bool, optional) – Run HLS co-simulation
validation (bool, optional) – Validate results between C-Sim and Co-Sim
csynth (bool, optional) – Run Coyote synthesis using Vivado, which will synthesize the model in a vFPGA
bitfile (bool, optional) – Generate Coyote bitstream
timing_opt (bool, optional) – Run additional optimizations when running PnR during bitstream generation
hls_clock_period (float, optional) – Clock period to be used for HLS synthesis
hls_clock_uncertainty (float, optional) – Clock uncertainty to be used for HLS synthesis

NOTE: Currently, the hardware will synthesize with a default clock period of 4ns / 250 MHz frequency, since this is the default frequency of Coyote (since the XDMA core defaults to 250 MHz). Coyote allows one to specify a different clock period for the model and use a clock-domain crossing (CDC) between the XDMA region and the model. This option is currently not exposed as part of the hls4ml backend, but advanced users can easily set in the the CMake configuration of Coyote.

NOTE: While the hardware will synthesize at 250 MHz, users can optionally pass a different HLS clock period This is primarily a work-around when HLS synthesize a kernel that doesn’t meet timing during PnR. The “trick” is to run HLS synthesis at a higher clock frequency then (or provide higher uncertainty)

TODO: Add functionality to parse synthesis reports

compile(model)

Compiles the hls4ml model for software emulation

Parameters:: model (ModelGraph) – hls4ml model to synthesize
Returns:: The name of the compiled library
Return type:: lib_name (str)

hls4ml.backends.coyote.coyote_overlay module

class hls4ml.backends.coyote.coyote_overlay.CoyoteOverlay(path: str, project_name: str = 'myproject')

Bases: object

CoyoteOverlay class, similar to NeuralNetworkOverlay for the VivadoAccelerator backend This class can be used to run model inference on the FPGA with the Coyote backend

predict(X: array, y_shape: tuple, batch_size: int = 1, verbose: bool = True)

Run model inference